Translation of data buffer from English into Chinese noun

The disadvantages of using resynchronization of high speed signalling are (i) increased chip complexity, area, power consumption, and cost, and (ii) increased delay through the isolator chip due to the necessary transmit data buffer.

In the coding of the program, every step is same as in previous program except the data buffer dbuf2, which we are using to handle the error generated by bad sector during the Disk reading operation and to maintain the size of the image file.

The sub-zones of the data buffer zone buffering the two I Frames respectively store the current I Frame and the earlier I Frame. When an I Frame is acquired in a data buffering process, the earlier I Frame is replaced.

The Keysight N6761A is a 50 W precision DC power module that provides low noise, and precise control and measurements in the milliampere and microampere region with the ability to simultaneously digitize voltage and current, and capture those measurements in an oscilloscope-like data buffer.

The input data control unit 42 operates as it receives the internal power supply voltages VIIR and VIIC. The input data control unit 42 outputs an input data signal DINZ received from the input data buffer 46 to the common data line CDBZ. An example of the input data control unit 42 is illustrated in FIG. 7.

On the basis of the data and the first ECC read from the NVM 300, the first ECC error detection block 230 detects an error in the data and the error correction block 280 corrects the detected error (step S922). The error-corrected data is held in the data buffer 210. Concurrently, the second ECC generation block 240 generates the second ECC for the data read from the NVM 300 (step S923). The second ECC thus generated is held in the second ECC buffer 250 (step S924). Because page access unit is greater than random access unit in which encoding is executed by the second ECC, the second ECC generation processing is repeated in order to generate two or more second ECCs (step S925). In an assumed example, 256-byte data is read by page access, so that eight second ECCs are generated on a 32 byte basis.

The read data bus switch RDBSW outputs the read data signal read to the common data line CDBZ to the output data latch circuit ODLT in a period when the read signal RDZ is at the high level (active). The output data latch circuit ODLT is the same as the command latch circuit CLAT illustrated in FIG. 7. The output data latch circuit ODLT receives the read data signal in the low-level period of the read clock signal RCLKZ, to latch the read data signal in synchronization with the leading edge of the read clock signal RCLKZ and output it as the output data signal DOUTZ to the output data buffer 44. The output data latch circuit ODLT latches the output of the common data line CDBZ in synchronized with the read out clock signal RCLKZ which changes H and L-level in burst length times.

As described above, for the data in the data buffer 210 with the write data reflected, the first ECC generation block 220 generates the first ECC (step S933). Concurrently, the second ECC in the second ECC buffer 250 is updated. Namely, if the second ECC corresponding to the data to be written is found in the second ECC buffer 250 (step S934), then the second ECC generation block 240 generates the second ECC in the unit of random access (step S935). The generated second ECC is held in the second ECC buffer 250 to be updated (step S936). If the second ECC has not been generated for all data to be written, the second ECC generation processing is repeated until all the second ECCs are generated (step S937).